CUDA: fuse FFN gate/up matmuls and GLU in MMQ with interleaved gate/up rows by anujj · Pull Request #29948 · ggml-org/llama.cpp
A new CUDA optimization in llama.cpp (PR #29948) fuses the FFN gate/up matrix multiplications and GLU activation within the MMQ kernel using interleaved gate/up weight rows. Benchmarks on a DGX Spark (GB10) system show 4…
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